SMARTMULTIPLY: DESIGN OF A LUT-BASED DSP MULTIPLIER FOR LOW BIT-WIDTH ARITHMETIC

Abstract

Digital Signal Processing (DSP) systems often require high-speed and area-efficient multipliers, particularly when operating on short wordlength data. Traditional multiplier architectures may consume significant hardware resources and power, making them less suitable for compact DSP applications. This study presents SmartMultiply, a Lookup Table (LUT)-based multiplier design optimized for low bit-width operations in DSP systems. The proposed architecture leverages precomputed multiplication results stored in LUTs, enabling rapid computation while minimizing resource utilization and propagation delay. Experimental evaluation demonstrates that SmartMultiply achieves faster multiplication, reduced power consumption, and lower area requirements compared to conventional multiplier designs, without compromising accuracy for short wordlength operations. The results highlight the potential of LUT-based approaches in improving performance and efficiency in compact DSP systems.